A computer's working memory, referred to as random access memory (RAM), provides storage of programs currently available to the system processor and the storage of data being processed. Also, the RAM provides storage of information displayed to the user. Typically, the working memory comprises dynamic random access memory ICs (DRAMS) due to their relatively low cost and high performance.
DRAMs require constant refreshing of their cells in order to maintain the data stored therein. Such refreshing occurs under the control of the memory controller. Various techniques for refreshing the memory cells are well known.
The refresh requirement of the DRAM cells consumes a relatively large amount of power. Such consumption of power poses a problem, particularly with portable computers since this requires larger battery capacity. One technique of reducing the power consumption is to a provide a "standby mode" of operating the computers. When in standby mode, the computer data in the DRAMs are not refreshed, thereby reducing power used by the system. The standby mode may be activated by various techniques such as by active, idle, or automatic entry.
One type of DRAM cell comprises a trench capacitor that is electrically coupled to a transistor. Trench capacitor DRAM cells are described in, for example, Wolf, Silicon Processing for the VLSI Era, Vol. 2, Lattice Press (1995), which is herein incorporated by reference for all purposes. In a NMOSFET type trench DRAM cell, the p-type well of the n-channel transistor is normally biased at a negative voltage to reduce substrate sensitivity and diffusion capacitance. Further, an n-type well, which is provided to electrically connect the buried plates of the capacitors, is typically biased at about V.sub.DD /2. Such DRAM cells, however, incur an increase in the flow of leakage current during standby mode. The increased flow of leakage current results in greater power consumption, which is undesirable and, in some cases, unacceptable.
From the above discussion, it is desirable to provide a standby mode of operation for DRAMs with reduced leakage current.